Differences Between SMARC 2.1.1 and SMARC 2.2
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Differences Between SMARC 2.1.1 and SMARC 2.2

SMARC 2.1.1 and SMARC 2.2 are two successive versions of the SMARC (Smart Mobility ARChitecture) embedded computer module standard. SMARC 2.2 is an evolutionary version of SMARC 2.1.1, designed to support newer, more powerful processor technologies while maintaining a high degree of backward compatibility.
Oct 29th,2025 665 Views

Differences Between SMARC 2.1.1 and SMARC 2.2

SMARC 2.1.1 and SMARC 2.2 are two successive versions of the SMARC (Smart Mobility ARChitecture) embedded computer module standard. SMARC 2.2 is an evolutionary version of SMARC 2.1.1, designed to support newer, more powerful processor technologies while maintaining a high degree of backward compatibility.

The following are the main differences between them, presented using a clear table and detailed explanations:

Overview of Key Differences

Feature SMARC 2.1.1 SMARC 2.2 Explanation of Changes
Release Year 2020 2025 Updated to adapt to new generation processors.
PCI Express Max. 1x PCIe x4 or 2x PCIe x1 Max. 2x PCIe x4 or 1x PCIe x4 + 2x PCIe x2 Key Difference. SMARC 2.2 significantly enhances PCIe lane configuration flexibility, supporting more high-speed peripherals.
Display Interface - 2x 24-bit LVDS
- 1x DDI (eDP/DP/HDMI)
- 1x MIPI-DSI (Optional)
LVDS natively removed
2x DDI (configurable as eDP/DP/HDMI)
1x MIPI-DSI (Mandatory)
Reflects the trend in display technology, shifting from traditional LVDS to modern eDP and MIPI-DSI.
USB 4x USB (2.0/3.0) 6x USB (at least 2x USB 3.0) Increased number of USB ports to meet the demands of more peripherals.
Storage 1x SATA, 1x SD/eMMC 1x SATA, 1x eMMC (Dedicated) Clarifies dedicated pins for eMMC, simplifying design.
Power Management ACPI-based ACPI-based, but with better support for modern SoC power states. Optimized support for new generation low-power processors.
Security Basic support Enhanced support for TPM (Trusted Platform Module) and Secure Boot. Adapts to growing security demands.
Pin Compatibility - Maintains mechanical and electrical compatibility Extremely Important: Carrier boards designed for SMARC 2.1.1 can typically use SMARC 2.2 modules directly, but may not support all new features.

Detailed Explanation

1. PCI Express Enhancement (The Most Significant Difference)

This is the core upgrade of SMARC 2.2.

  • SMARC 2.1.1: Provided one set of PCIe x4 lanes, which could alternatively be split into two PCIe x1 lanes. This was sufficient at the time but could become a bandwidth or port count bottleneck for applications requiring multiple high-speed interfaces (e.g., multiple Gigabit Ethernet ports, NVMe SSD, high-speed frame grabbers).

  • SMARC 2.2: Provides two independent PCIe x4 lane configurations. This means the module can simultaneously offer:

    • Two PCIe x4 interfaces, OR

    • One PCIe x4 interface plus two PCIe x2 interfaces.
      This flexibility allows designers to connect two high-speed devices (e.g., an NVMe SSD and a 10 Gigabit Ethernet card) simultaneously without needing a PCIe switch on the carrier board, thereby reducing system complexity and cost.

2. Display Interface Modernization

This reflects the embedded market's shift from traditional to modern display interfaces.

  • SMARC 2.1.1: Still retained two 24-bit LVDS interfaces for compatibility with older panels still in use. It also provided one DDI (Digital Display Interface, configurable as eDP, DP, or HDMI) and one optional MIPI-DSI.

  • SMARC 2.2: Directly removes the LVDS interface. It is replaced by:

    • Two full DDI interfaces: Each can be independently configured as eDP, DP, or HDMI. This supports connecting two high-resolution displays.

    • One mandatory MIPI-DSI interface: Due to the prevalence of smartphones and tablets, MIPI-DSI has become the mainstream interface for small, low-power displays, and SMARC 2.2 makes it a standard feature.

3. USB and Other I/O Expansion

  • USB: Increased from 4 to 6 ports, with a clear mandate that at least two must be USB 3.0 or faster, accommodating more and faster peripherals.

  • Storage: Clarified dedicated pins for eMMC flash, separating it from the SD card interface for a cleaner design.

4. Backward Compatibility

This was a crucial design goal. The SMARC 2.2 specification ensures:

  • Mechanical Compatibility: The module's dimensions, screw holes, and connector positions are identical.

  • Electrical Compatibility: The definitions of power pins and basic signal pins remain consistent.

This means that a carrier board designed according to the SMARC 2.1.1 standard can typically have a SMARC 2.2 module plugged in, boot, and function normally. However, the carrier board will be unable to utilize the new features of SMARC 2.2, for example:

  • The second PCIe x4 interface will be unavailable.

  • The second DDI display output may not work.

  • The additional USB ports may not be connected.

To fully leverage all the new features of a SMARC 2.2 module, a new carrier board must be designed.

Summary and Selection Advice

  • SMARC 2.1.1: Suitable for designs based on older processors (such as Intel Atom E3900 series, early i.MX6/8) or for projects where the application scenario does not require multiple high-speed PCIe lanes and modern display interfaces. It is a mature and widely deployed standard.

  • SMARC 2.2: Is the future-proof choice. It is specifically designed for new generation high-performance, low-power ARM and x86 SoCs (such as Intel 11th Gen Tiger Lake, AMD Ryzen Embedded R-series, NXP i.MX8/9, Renesas RZ/G2L, etc.). You should choose it if you need:

    • Higher I/O bandwidth (multiple high-speed PCIe lanes).

    • Support for dual high-resolution displays or modern MIPI displays.

    • More USB interfaces.

    • Stronger security.

Conclusion: For new projects, it is highly recommended to select modules conforming to the SMARC 2.2 standard, as it better supports current and future processor technologies and provides greater expansion capabilities. If upgrading an existing SMARC 2.1.1 system, module replacement can be seamless, but a carrier board redesign is required to unlock its full performance.

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